"BRIDGE THE GAP BETWEEN ALGORITHM & REAL CIRCUITS"
FIR FILTERS
GENERAL FIR
PROGRAMMABLE FIR
LOWPASS FIR
HIGHPASS FIR
BANDPASS FIR
BANDSTOP FIR
HALFBAND LOWPASS FIR
MULTIRATE LOWPASS FIR
HALFBAND HIGHPASS FIR
IIR FILTERS
GENERAL IIR
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CIC SINGLERATE
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DDS/NCO
PHASE TO SIN/COS
DDS-NCO
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Within a short period of time, we will send you resource and power numbers for requested IP, and make arrangements for delivery of the IP in the desired form.
Our IP can be targeted at any FPGA, or any
ASIC geometry, technology, and library. Please contact us for details.
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IMPLEMENTING LOWEST POWER DIGITAL DATAPATHS IN DAYS NOT WEEKS
By using standard and proprietary datapath IP and evolutionary optimization algorithms.
IMPLEMENTING LOWEST
POWER DIGITAL
DATAPATHS
IMPLEMENTING LOWEST RESOURCE AND HIGHEST THROUGHPUT FPGA DATAPATHS
IN DAYS NOT WEEKS
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For other datapath blocks not listed above, email us specs in ANY form (i.e. matlab, c, verilog, document)
GATeIC was founded with a mission to help the semiconductor industry transition from analog to digital domains by creating tools and technologies that help engineers create cost, time, and technically optimal IP with the push of a software button, not in days or weeks, but hours.
Since our founding, the company has made significant progress in developing ground breaking technologies, both in software and digital IP implementations. In 2008, GATeIC’ introduced GICWare - a set of industry leading low-power digital datapath IP, and GICShell - IP specification, optimization, and exploration platform, which establishes a new category for EDA platforms. The platform includes our ground breaking IP Constellation Generator, which takes system level specifications for digital components, and generates a constellation of practically tape-out ready implementations. The engineer can then select the optimal implementation, based on area-power, area, performance, or other trade-offs.
JACK GIFFORD
1941-2009
Jack Gifford was one of the pillars of Silicon Valley, who shaped the semiconductor industry with his vision and the companies he created. As a founding member of AMD and Maxim Integrated Products, he holds the distinction of founding two of the most successful semiconductor companies in the world.
Jack was a early investor and mentor, who inspired our team to set our sights high, and focus on developing groundbreaking technologies. We honor Jack's memory by continuing his work in the industry he loved.
GARY MEKIKIAN
Dr. ARTHUR TOROSYAN
TIGRAN MEKIKIAN
DIGITAL FIR FILTERS
DIRECT DIGITAL SYNTHESIZER
MODULATORS
GICShell
FILTER DESIGN SHELL
DDS NCO DESIGN SHELL
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Our GICShell platform offers push button specification, design, trade-off analysis, design selection, and implementation of digital IP. The Filter Design module can generate tens of digital filter designs as part of IP exploration process.
We also offer GDSII consulting services to ensure a smooth transition of IP into the overall design. Even though GICShell generates industry leading IP, GATeIC offers custom design services to further tune and optimize our IP, or create new IP based on the customer's specifications.
GATeIC has developed ultra-low power solutions for various commonly used signal processing blocks based on its patent-pending technologies. Using new technologies and algorithms the company has produced signal processing cores that significantly reduce power consumption while simultaneously delivering high performance. We now have industry leading designs for ultra-low-power Direct Digital Synthesizers and Digital Filters. We are developing next generation decoders, modulators and FFTs.
IC DESIGN
OPTIMALITY
Pasadena, Calif. - On the heels of delivering groundbreaking digital IP in April, GATeIC completed yet another digital sub-system design for a mixed signal, high-speed IC, proving once again that its process and SoftGATe suite of proprietary automation tools converge on optimal designs for digital components. This time, GATeIC engineers were able to explore IP at the block level and consider corresponding system level optimizations within a week of finalizing the specs. On an IC that has been in the market in multiple generations, the SoftGATe platform churned through 5.8 million combinations to help engineers arrive at a final design that saved a minimum of 40% power while reducing area by more than 10%, as compared to the latest iteration of the IC. The IC is implemented in TSMC 180 nanometer CMOS process.
Pasadena, Calif. - GATeIC delivers 8 High Speed Digital Data Path Blocks In Less Than 4 Weeks. Collaborating with one of the largest Semiconductor IC companies in the world, GATeIC completed the delivery of interpolating filters and high resolution Direct Digital Synthesizers for an important IC, saving 40%+ in power in record time (less than 4 weeks) while eliminating DC bias and minimizing coupling noise. GATeIC used its proprietary IP Configuration and Exploration tools to quickly configure and evaluate hundreds of different architectures in the area vs. power vs. timing closure space, and provided candidate architectures for each block for final evaluation and selection. The results saved time, money, and engineering resources while lowering power and increasing operating guarantees for the IC.
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Go from specs to implementation
in days for custom ASIC DSP blocks
Written by: Richard Nass
SOFTGATE OPTIMIZES
DATA PATH
Written by: Nicolas Mokhoff
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Digital filtering is one of the most widely used operations in digital signal processing applications. A digital filter accepts an input signal and performs filtering (or signal conditioning) to generate the output signal. The specific signal conditioning performed by the filter depends on the filter's frequency response. Actual realization of a digital filter requires multiple phases, beginning with the design of the filter impulse response, continuing with the architectural realization of the filtering operation, and completing with the actual hardware implementation.
GATeIC's filter design engine runs optimization routines to minimize the filter order and coefficient bitwidth while satisfying the filter specification. GATeIC's filter implementation architectures provide area and power efficient designs specific for the implementation technology.
Digital filters are found in numerous applications, some of which are listed below:
Digital Communications (wireless, wireline), Image, Processing, Audio Processing, Equalization, Sample-Rate Conversion, Anti-Aliasing and Image Removal, Bioengineering, Medical equipment.
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Direct Digital Synthesizer (DDS) generates the samples of sine and cosine functions having the precise frequency dictated by the input frequency control word (fcw). It consists of a phase accumulator and a phase-to-amplitude converter. The phase accumulator generates a sequence of phase angle values from the input fcw while the phase-to-amplitude converter produces the sine and cosine samples of the corresponding phase angles produced by the phase accumulator. As the value of the input fcw is increased or decreased, the frequency of the sine and cosine functions represented by the DDS output samples is increased or decreased, respectively. The challenge in designing DDS lies in the efficient design of the phase-to-amplitude converter without introducing large errors to the output samples. The advantages offered by DDS over alternative frequency synthesis methods are; instantaneous settling time, fast and continuous-phase switching response, very fine (virtually limitless) frequency resolution, large bandwidth, low phase noise, excellent spectral purity, and ease of integration with other digital blocks.
Given a set of DDS performance and design specifications, GATeIC's DDS architectures provide efficient implementations for the DDS while meeting the specified specifications. GATeIC's architectures offer far superior efficiency when compared to the traditional lookup table or CORDIC DDS implementations, resulting in significant area and/or power savings.
Sine and cosine functions play a fundamental role in science and engineering. As a result, DDS spans a large range of applications.
* Digital Communications (wireless, wirelines, optical)
* Wireless Base Stations
* Fast Frequency Hopping Systems
* Radar and Scanning Systems
* Local Oscillator [LO] Synthesis
* Clock Generation
* Test and Measurement Equipment
* Medical Equipment
* Particle Accelerators
The performance characteristics of the DDS depend on the accuracy with which the DDS output samples represent the ideal sine and cosine functions. The quality of the DDS block is captured by metrics computed from the Fourier Transform of the DDS outputs. Since the Fourier Transform of an ideal sine and cosine function is a pure tone, the impurities from all errors sources contributing at the DDS output are conveniently captured by the resulting spurious components (i.e., spurs) of the DDS output Fourier Transform. The commonly used metrics for specifying the DDS output quality are the Spurious-Free Dynamic Range (SFDR) and Signal-to-Noise Ratio (SNR). SFDR is the measure of the largest-magnitude spur relative to the magnitude of the desired tone. SNR is the measure of the noise power due to all spurs relative to the power of the desired tone. The following illustrates a performance characteristic for a DDS having 13-bit outputs and using phase-truncation down to 18 bits (i.e., W = 18).
With GATeIC's GICShell™ platform, estimating is no longer necessary to converge on optimal designs for a given digital block. GICShell assists the engineer to find the “optimum” design by offering a constellation of implementations at the push of a software button.
The platform then takes these implementations through the engineer's physical design flow automatically to produce precise measurements for performance, timing, area, and power, and gives the engineer the freedom to choose whichever design is considered to be “optimal”. GICShell automates the entire process of specifying, designing, and implementing practically tape-out-ready silicon, while making the process error free, and eliminating the need for prohibitive amounts of time and expense to perform accurate tradeoff analysis across multiple implementations.
The software runs on any one of the Linux platforms, and is fully integrated with implementation flow tools. It offers a web based graphical dashboard, and TCL base command line interface and scripting capabilities.
Send us an email at to request a test drive of GICShell in Software as a Service mode. We will send you a username and password, as well as instructions on how to login and use the system.
GICShell can be used by a filter design engineer to quickly generate tens of candidate designs for a specific digital filter.
GATeIC's GICShell and GICWare offer industry leading low-power digital filters that can reduce power consumption of some data path SoCs by as much as 50%. We empower the design engineer to go from system level design specification, to multiple design considerations, and selection of practically tape-out ready optimal design in a matter of hours. This process includes the filter design (i.e., the impulse response generation in the case of an FIR filter), synthesis, placement, routing, parasitic extraction, post-place-and-route timing and power analysis based on vector simulations to capture accurate signal toggling activities. For design organizations that lack the tools to perform place and route, GICShell offers a prototyping mode, where the designs are only synthesized and timing, power, and area metrics are measured from the post-synthesis netlist. Power consumption is again measured using a vector-based simulation.
Whether you are implementing FPGA's, designing SoCs, or chips for communication, consumer, medical , or other applications, GICShell and GICWare can help reduce the cost, time, and engineering expertise required to design the major digital components that make up the datapath. You can also use GICShell to see if fab cost savings can be achieved by replacing legacy designs with more area efficient modern designs.
Since Filter Design module is built on the GICShell platform, it offers the designer all the capabilities of a Linux and TCL based shell command interaction and scripting environment. The tool comes with a set of scripts that can be easily modified by the engineer to perform filter design runs by an execution of a single shell command. GICShell's scripting environment enables compatibility and full integration with ECAD tools such as Synopsys, Cadence, Magma, and others, all within the GICShell environment.
Since DDS module is built on the GICShell platform, it offers the designer all the capabilities of a Linux and TCL based shell command interaction and scripting environment. The tool comes with a set of scripts that can be easily modified by the engineer to perform filter design runs by an execution of a single shell command. GICShell's scripting environment enables compatibility and full integration with ECAD tools such as Synopsys, Cadence, Magma, and others, all within the DDSGIC environment.
Whether you are designing SoCs or chips for communication, consumer, medical , or other applications, GICShell and GICWare can help reduce the cost, time, and engineering expertise required to design the major digital components that make up the chip. Specs to GDSII can be achieved within hours.
GICShell's DDS module generates industry's leading custom, low-power, DDS implementations. It is a fully integrated design and implementation tool that empowers the design engineer to go from system level design specification, to multiple design considerations, and selection of practically tape-out ready optimal design in a matter of hours. This process includes the DDS design based on specifications, synthesis, placement, routing, parasitic extraction, post-place-and-route timing and power analysis based on vector simulations to capture accurate signal toggling activities. For design organizations that lack the tools to perform place and route, GICShell offers a prototyping mode, where the designs are only synthesized and timing, power, and area metrics are measured from the post-synthesis netlist. Power consumption is again measured using a vector-based simulation.
Gary has over 20 Years of technology, entrepreneurship, and management experience. In addition to co-founding GATeIC, Gary is a Partner at Silicon Valley Technologies, LLC, a Stanford, California based technology firm he founded with professors from Stanford University.
Gary is a member of Stanford Sloan Alumni Board at the Graduate School of Business, and collaborates with business school professors William P. Barnett and John D. Roberts on developing business cases.
Previously Gary was Chairman and CEO of answerFriend Inc. (now Inquira), a privately held Customer Relationship Management software company he founded with MIT PhD graduates. The company uses natural language processing technology, and was featured in the Wall Street Journal and Fortune business publications for its far advanced technology.
In 1993, Gary was a co-founder of a successful IT services company, International Integration Inc. ("i-Cube"), which went public in 1998, and was later acquired by Razorfish Inc. Gary also held marketing and engineering positions at Hewlett-Packard Company.
Gary received his BS in Electrical Engineering from the University of Southern California, and his MS from Stanford University. He is a Sloan Fellow at the Stanford Graduate School of Business.
Dr. Arthur Torosyan co-founded GATe Integrated Circuits, Inc. where he leads the technical developments for efficient design and implementation of signal processing circuits based on a new patent-pending technology. Between 2000 and 2005 Art has been a technical consultant for Pentomics, Escape Communications, and Parabellum, specializing in the design and analysis of digital integrated circuits and systems. From 1997 to 2000 he was with Northrop Grumman (TRW), where he worked on hardware design, analysis, and development of digital satellite communications systems.
Art received his B.S degree in Electrical Engineering and Computer Science from MIT in 1997, and his M.S and Ph.D. degrees in Electrical Engineering from UCLA in 2001 and 2003, respectively. He was awarded the Edward K. Rice 2003 School of Engineering Outstanding Doctoral Student Award, the Intel Corporation Ph.D. Fellowship award for 2001-2002, the UCLA Outstanding Graduate Student awards in 2001 and 2002, and the TRW Graduate Fellowship award for 1997-2000.
Art has taught the EE212A graduate level class (Theory and Design of Digital Filters) at the UCLA Graduate School of Electrical Engineering.
Member of IEEE Communication Society.
Mr. Tigran Mekikian leads the company's marking, finance and administration activities. He brings years of finance and operations experience to GATeIC.
Most recently as President of Opes Financial Solutions, LLC., Tigran managed the marketing, vendor relations, and banking relationships. Prior to Opes Financial, Tigran managed the Sales and Marketing efforts at Spaulding Capital, as well as establishing Large Vendor with fortune 1000 companies.
Tigran pursued a legal education at Whittier Law School in Costa Mesa, in addition to earning his Bachelors Degree from the University of Southern California.
DESCRIPTION: General FIR | Single-Rate or Multi-Rate | Fixed or Programmable, Real or Complex-Valued Coefficients |
DOWNLOAD SPEC SHEET
(click on image)
general fir v 1.1
DESCRIPTION: FIR | Single Rate | Arbitrary Magnitude/Phase | Programmable Real or Complex valued Coefficients |
programmable fir v 1.5
DOWNLOAD SPEC SHEET (click on image)
DESCRIPTION: FIR | Singlerate | Lowpass | Fixed Real-Valued Coefficients |
lowpass fir v 1.5
DESCRIPTION: FIR | Singlerate | Highpass | Fixed Real-Valued Coefficients |
highpass fir v 1.5
DESCRIPTION: FIR | Singlerate | Bandstop | Fixed Real-Valued Coefficients |
bandstop fir v 1.5
DESCRIPTION: FIR | Singlerate | Bandpass | Fixed Real-Valued Coefficients |
bandpass fir v 1.5
DESCRIPTION: FIR | Rate single, decimate or interpolate by 2 | Lowpass | Fixed Real-Valued Coefficients |
halfband
DESCRIPTION: FIR | Rate: single, decimate or interpolate by 2 | Highpass | Fixed Real-Valued Coefficients |
DESCRIPTION: FIR | Multirate, Interpolation or Decimation | Lowpass | Fixed Real-Valued Coefficients |
multirate
DESCRIPTION: General IIR | Single-Rate or Multi-Rate | Fixed or Programmable, Real or Complex-Valued Coefficients |
general iir v 1.1
DESCRIPTION: Phase to Sin/Cos Amplitude Converter | Quadrature, Sin or Cosine only, Sine or Cosine selectable |
phase to sincos v 1.3
DESCRIPTION: DDS/NCO | Quadrature, Sin or Cosne only, Sine or Cosine selectable | Optional Phase Offset and/or Amplitude Scaling
dds-nco v 1.3
DESCRIPTION: CIC(FIR) Fixed or Selectable Interpolation | Lowpass | Fixed or Selectable M, number of stages | Real or Complex I/O |
cic interpolator v 1.3
DESCRIPTION: CIC (FIR) | Fixed or Selectable Decimation | Lowpass | Fixed or Selectable M, number of Stages | Real or Complex I/O
cic decimator v 1.3
DESCRIPTION: CIC (FIR) | Single Rate | Lowpass | Fixed or Selectable M, number of Stages Real | Real or Complex I/O
cic singlerate v 1.3
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